Nice Area, France
ASIC Verification Principal Application Engineer at Cadence Design Systems
Semiconductors
Education
Universite de Aix-Marseille I 2002 — 2003
Master of Science (M.Sc.), Microelectronics in wireless systems
Université de Nice-Sophia Antipolis 2000 — 2002
Master, Electrical, Electronics and Telecommunications Engineering
IUT Nice 1998 — 2000
Bachelor of Engineering (BEng), Industrial Electronics Technology/Technician
Experience
Cadence Design Systems July 2014 - Present
Cadence Design Systems July 2012 - September 2014
Cadence Design Systems March 2010 - June 2012
NXP Semiconductors November 2007 - February 2010
Texas Instruments November 2006 - November 2007
STMicroelectronics April 2006 - November 2006
philips semiconductors June 2005 - March 2006
Texas Instruments August 2004 - April 2005
Scaleo chip April 2003 - September 2003
Skills
Palladium, Ethernet, Virtual Prototyping, Git, Agile Methodologies, Emanager, Functional Verification, Hardware Architecture, incisive, SystemC, DesignSync, OCP, Digital Signal..., TLM, C++, mercurial, DDR3, ASIC, PSL, USB3.0, High Level Synthesis, System Testing, PCIe, Microprocessors, Training Delivery, JTAG, Verilog, VIP, VHDL, Salesforce.com, OMAP, jenkins, I2C, Unix Shell Scripting, AMBA, Open Verification..., UVM, Linux, Bluetooth, ClearCase, Problem Solving, Formal Verification, Eclipse, Semiconductors, Perl, SystemVerilog, SoC, Extreme Programming, Specman, Debugging