Grenoble Area, France
Senior CAD Engineer at ARM
Semiconductors
Education
University of Lyon, France
Experience
ARM June 2011 - Present
ASTUS January 2010 - June 2011
Cadence Design Systems November 1999 - March 2009
Skills
Perl, Physical IPs, CMOS, SKILL/SKILL++, Multiple Patterning, SoC, DRM, Microelectronics, LVS, DRC, Hercules/ICV/StarRC, Synchronicity, PDK Development, EDA, Bulk, Cadence Virtuoso, Pcells/Pycells, Cadence, CAD, Physical Verification, Shell Scripting, Analog, Parasitic Extraction, Virtuoso ICADV12.2, Physical Design, Calibre..., Diva/Assura/PVS/QRC, Simulation, Spectre, VLSI, FinFET, Foundries, Tcl, RF, DFM, AMS IC Design Flows, SOI, PDK Validation, PDK Support, Integrated Circuit..., ARM, ASIC, Circuit Design, Semiconductors, UNIX/Linux, Advanced nodes, C/C++, Python, HSPICE, Mixed Signal