Nice Area, France
FPGA/SoC architect / verification
Semiconductors
Education
Cergy-Pontoise University 2007 — 2011
Doctor of Philosophy (PhD), embedded computer's architecture, many honors
IFSIC 2003 — 2003
DEA, Artificial Inteligence and Image processing, speciality Processor Architecture Optimisation
ENSSAT 2001 — 2003
Ingénieur Télécom Système Informatisés, microélectronics / Industrial computing / IA / Machine learning / Real time systems
Lycée Marie Curie 1995 — 1998
French Baccalauréat S, Math, Physics, Biology
Experience
Elsys Design 2011 - Present
SuperSonic Imagine August 2014 - April 2015
Thales TRT - HPC Lab / ETIS lab - CNRS (UMR8051) 2007 - 2011
Skills
Embedded Software, Architecture, SystemC, Verilog, embedded HPC, RTOS, clearcase, Software Development, Architecture systèmes, System Architecture, UML, VHDL, Reconfigurable Computing, Unix, Linux, MPSoC, DO254, RTEMS, ArchC ADL, C, C++, Telecommunications, Subversion, Configuration Management, Perl, UVM, Verification, µC-OS II, Tcl, Testing, VLIW, Développement de..., ARM, FPGA, MS Project