France
Assistant Professor at Supelec
Research
Education
Telecom ParisTech 2008 — 2011
PhD, Communication and Electronics
Universidade Federal do Rio Grande do Sul 2008 — 2008
Master, Cadence Certification
Universidade Federal do Rio de Janeiro 2006 — 2008
M.Sc., Electric Eng., Microelectronics
Universidade Federal do Rio de Janeiro 2002 — 2006
B.Sc., Electronic Eng.
Universidade Estadual de Campinas 2006 — 2006
Summer Course, Microelectronics Workshop and MOS's Manufacture
Experience
Supelec September 2014 - Present
University of Lille 1 November 2013 - August 2014
ISEN-Lille September 2012 - August 2013
IM2NP-UMR 7334, Université d'Aix-Marseille, France December 2011 - August 2012
Telecom ParisTech October 2008 - September 2011
TELECOM ParisTech September 2009 - May 2011
Analog and Digital Signal Processing Laboratory (PADS) March 2003 - February 2008
UFRJ IEEE Student Branch June 2003 - December 2007
UFRJ March 2007 - July 2007
UFRJ March 2006 - August 2006
Skills
Verilog-A, Analog Design, Altera Quartus, Cadence, Programming, Mixed Signal, French, Verilog, Simulation, Teaching, Eldo, Microelectronics, ASIC, VHDL, Wireless Communications..., C, PCB design, C++, FPGA, Physics, Modeling, Matlab, ModelSim, Analog Circuit Design, Image Processing, Electronics, SystemC, CMOS, Embedded Systems, Algorithms, Language Development, English, Microcontrollers, LaTeX, RF, Mathematical Modeling, Language Skills, Simulations, Python, Digital Signal..., Research, SoC, Cadence Virtuoso, Spectre, Analog, Signal Processing, Semiconductors, IC, EDA, Xilinx ISE