Italy
R&D CAD AMS design & verification AE
Electrical/Electronic Manufacturing
Education
Polytechnic of Milan 1998 — 2005
Master's degree
CDS
High School Bisuschio
Experience
STMicroelectronics November 2005 - Present
CEFRIEL August 2005 - September 2005
I.S.U. Politecnico Milano January 2004 - December 2004
Skills
EDA, Simulations, SPICE, Analog Circuit Design, Virtuoso, ModelSim, Microprocessors, Integrated Circuit..., LVS, Circuit Design, Functional Verification, Processors, Analog, Mixed Signal, Hardware Architecture, ASIC, Clock Tree Synthesis, Digital Signal..., CMOS, SystemVerilog, Static Timing Analysis, TCL, Semiconductors, Low-power Design, Embedded Systems, Timing Closure, Electrical Engineering, Physical Design, PLL, VLSI, Electronics, Parasitic Extraction, IC, VHDL, Power Management, NCSim, DRC, Physical Verification, SoC, Semiconductor Industry, Cadence Virtuoso, Primetime, Verilog, Dynamic Simulation, Spectre, Microcontrollers, Embedded Software, Microelectronics