Netphen, Nordrhein-Westfalen, Germany
Digital Design and Verification Engineer
Semiconductors
Education
Universität Siegen 2013 — 2015
Master's Degree, Mechatronics Engineering
Mahrishi Dayanand University 2006 — 2010
Bachelor's Degree, Electronics and Communication Engineering
Experience
Universität Siegen May 2015 - Present
Quh-Lab Lebensmittelsicherheit October 2014 - March 2015
University of Siegen February 2014 - August 2014
Synopsys September 2011 - October 2012
nSys Design Systems May 2010 - September 2011
Skills
Computer Architecture, Semiconductors, VHDL, Electronics, Digital Electronics, Cadence Virtuoso, PCIe, Embedded Systems, Perl, SoC, FPGA, Logic Design, RTL coding, VLSI, UVM, Microcontrollers, Formal Verification, Matlab, VMM, Linux, ARM, ASIC, Verilog, Functional Verification, Open Verification..., ModelSim, TCL, Specman, EDA, Physical Design, Simulations, Static Timing Analysis, RTL design, Algorithms, Debugging, Integrated Circuit..., SystemC, C++, Programming, C, Xilinx, SystemVerilog, Ethernet, Hardware, NCSim, AXI, Hardware Architecture, AMBA AHB, LabVIEW, Altera Quartus