Munich Area, Germany
Digital ASIC Implementation and DFT Consultant at Freelancer
Semiconductors
Education
Tel Hai College 1995 — 1997
Practical Engineer, Electronic Engineering
Experience
Freelancer January 2014 - Present
MATIS Deutschland GmbH February 2011 - December 2013
Siemens AG November 2009 - January 2011
Indepedent Freelancer February 2009 - October 2009
Cadence Design Systems June 2006 - January 2009
Cadence Design Systems May 2004 - January 2009
Avnet Electronics November 2001 - October 2003
AST September 2000 - October 2001
AST October 1997 - September 2000
Skills
Signal Integrity, Timing, Hardware Verification, RTL coding, Digital Design, ModelSim, Logic Design, Route, Boundary Scan, Low Power Design, Semiconductors, TCL, RTL design, Timing Closure, Backend, EDA, SoC, ic, ATPG, MS Project, DFT, NCSim, Floorplanning, FPGA, Circuit Design, VHDL, CPLD, DRC, Clock Tree Synthesis, Formal Verification, Layout, Physical Verification, JTAG, Programming, LVS, Physical Design, VLSI, Physical implementation, NC-Verilog, Xilinx, Linux, VCS, unix, Functional Verification, Primetime, Static Timing Analysis, Power Analysis, Simulation, ASIC, Debugging